RISC-V: SMP cleanup and new features
authorPalmer Dabbelt <palmer@sifive.com>
Tue, 23 Oct 2018 00:39:29 +0000 (17:39 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 23 Oct 2018 00:41:43 +0000 (17:41 -0700)
commitd26c4bbf992463c043fdee4b3e5efa3f08990862
tree6f7eb8b1da031352fc3e386dd4662fabf132b942
parenta6de21baf6373ac1ddd5c52e8fbd959f164ef9cf
parent8b20d2db0a6d2761e0fc156eb74f7a55b92b3147
RISC-V: SMP cleanup and new features

This patch series now has evolved to contain several related changes.

1. Updated the assorted cleanup series by Palmer.
The original cleanup patch series can be found here.
http://lists.infradead.org/pipermail/linux-riscv/2018-August/001232.html

2. Implemented decoupling linux logical CPU ids from hart id.
Some of the work has been inspired from ARM64.
Tested on QEMU & HighFive Unleashed board with/without SMP enabled.

3. Included Anup's cleanup and IPI stat patch.

All the patch series have been combined to avoid conflicts as a lot of
common code is changed different patch sets. Atish has mostly addressed
review comments and fixed checkpatch errors from Palmer's and Anup's
series.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/kernel/entry.S
arch/riscv/kernel/setup.c