[X86] Change PMULLD to 10 cycles on Skylake per Agner's tables and llvm-exegesis.
authorCraig Topper <craig.topper@intel.com>
Tue, 20 Mar 2018 23:39:48 +0000 (23:39 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 20 Mar 2018 23:39:48 +0000 (23:39 +0000)
commitd25f1acf6713752b7ec47309b3f7733ba61fa330
treeb50d20cec6e85853ccdf6ff6f8677d0469a28ac2
parentbb059deacb8d538cf3ff14edc37e892c4301f558
[X86] Change PMULLD to 10 cycles on Skylake per Agner's tables and llvm-exegesis.

Also restrict to port 0 and 1 for SkylakeClient. It looks like the scheduler models don't account for client not having a full vector ALU on port 5 like server.

Fixes PR36808.

llvm-svn: 328061
llvm/lib/Target/X86/X86SchedSkylakeClient.td
llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/test/CodeGen/X86/avx2-schedule.ll
llvm/test/CodeGen/X86/avx512-schedule.ll
llvm/test/CodeGen/X86/sse41-schedule.ll