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DEVICETREE: Add bindings for the ATH79 DDR controllers
authorAlban Bedel <albeu@free.fr>
Sat, 30 May 2015 23:52:26 +0000 (01:52 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Sun, 21 Jun 2015 19:54:02 +0000 (21:54 +0200)
commitd25b4f65bf7608ba7f59d3f0251ea57e34b74238
tree5e147f6167fcb3fd5e569fe22a6bdd26ea981945tree | snapshot
parent03c8c407a8c9ba1772ea7c086b7a0f7bceecdb65commit | diff
DEVICETREE: Add bindings for the ATH79 DDR controllers

The DDR controller of the ARxxx and AR9xxx families provides an
interface to flush the FIFO between various devices and the DDR.
This is mainly used by the IRQ controller to flush the FIFO before
running the interrupt handler of such devices.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt [new file with mode: 0644] blob
Domain: System / Kernel;