clk: agilex: Additional membus writes for HPS PLL
authorChee Hong Ang <chee.hong.ang@intel.com>
Fri, 10 Jul 2020 12:55:23 +0000 (20:55 +0800)
committerLey Foon Tan <ley.foon.tan@intel.com>
Fri, 9 Oct 2020 09:53:10 +0000 (17:53 +0800)
commitd24f2bc1481323b37b056522b3b246ee2d59a943
tree91bfc556a3da45728269bdf3eb44506b5d10f9a5
parent35d847ed908d3b1d6e58d95b3b9f326111343df5
clk: agilex: Additional membus writes for HPS PLL

Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
drivers/clk/altera/clk-agilex.c