ppc4xx: Fix chip select timing for SysACE access on AMCC Katmai
authorStefan Roese <sr@denx.de>
Thu, 19 Apr 2007 07:53:52 +0000 (09:53 +0200)
committerStefan Roese <sr@denx.de>
Thu, 19 Apr 2007 07:53:52 +0000 (09:53 +0200)
commitd21686263574e95cb3e9e9b0496f968b1b897fdb
tree72168ce39342ee47d4388b824710441ad1776176
parentafc7e4c2a4729427bec672561ea1b3dbb5e8c0d3
ppc4xx: Fix chip select timing for SysACE access on AMCC Katmai

Previous versions used full wait states for the chip select #1 which
is connected to the Xilinix SystemACE controller on the AMCC Katmai
evaluation board. This leads to really slow access and therefore low
performance. This patch now sets up the chip select a lot faster
resulting in much better read/write performance of the Linux driver.

Signed-off-by: Stefan Roese <sr@denx.de>
include/configs/katmai.h