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(parent: c228cb3) | patch
nv50/nir: align tlsspace to 0x10
authorKarol Herbst <kherbst@redhat.com>
Mon, 25 Apr 2022 20:21:16 +0000 (22:21 +0200)
committerMarge Bot <emma+marge@anholt.net>
Fri, 29 Apr 2022 23:07:03 +0000 (23:07 +0000)
commitd1ff453a0dfdbcc9d23ad1992487530bcab9994d
tree534d4ce132d2f4287bda5189e4890600944521e9tree | snapshot
parentc228cb388956ce3acd8cec71e4de25b6e0a738ddcommit | diff
nv50/nir: align tlsspace to 0x10

nvc0 aligns to 0x10 in setting up its rogram header, but nv50 TLS
allocation expects the incoming value to be aligned already (like TGSI
always did).  Avoids regression in
KHR-GL33.shaders.arrays.declaration.dynamic_expression_array_access_* with
the nir backend.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp diff | blob | history
Domain: Graphics System / GL;