drm/i915/icl: Configure DSI transcoder timings
authorMadhav Chauhan <madhav.chauhan@intel.com>
Mon, 15 Oct 2018 14:28:03 +0000 (17:28 +0300)
committerJani Nikula <jani.nikula@intel.com>
Mon, 22 Oct 2018 12:14:40 +0000 (15:14 +0300)
commitd1aeb5f399d98443fd1f4b26480519379cb9cec8
tree7ee067747b317fa42573b8718df7a813c78678b5
parent7b56caf36376f6d714a56ae42865da0a5ef7b2fc
drm/i915/icl: Configure DSI transcoder timings

As part of DSI enable sequence, transcoder timings
(horizontal & vertical) need to be set so that transcoder
will generate the stream output as per those timings.
This patch set required transcoder timings as per BSPEC.

v2: Remove TRANS_TIMING_SHIFT usage

v3 by Jani:
 - Rebase
 - Reduce temp variable use
 - Checkpatch fix

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/525949ae4e919a4f2b807d606234322534656048.1539613303.git.jani.nikula@intel.com
drivers/gpu/drm/i915/icl_dsi.c