clk: tegra20: Turn EMC clock gate into divider
authorDmitry Osipenko <digetx@gmail.com>
Sun, 21 Oct 2018 18:30:50 +0000 (21:30 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sun, 1 Dec 2019 08:17:28 +0000 (09:17 +0100)
commitd15b8b691725a432130358d198e909ccb48b403b
tree61daca3142937dfee8461e8fefbb8dc32c770d38
parent91c5f99d131ed3b231aaef7d4ed6799085b095a3
clk: tegra20: Turn EMC clock gate into divider

[ Upstream commit 514fddba845ed3a1b17e01e99cb3a2a52256a88a ]

Kernel should never gate the EMC clock as it causes immediate lockup, so
removing clk-gate functionality doesn't affect anything. Turning EMC clk
gate into divider allows to implement glitch-less EMC scaling, avoiding
reparenting to a backup clock.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/tegra/clk-tegra20.c