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re PR rtl-optimization/71621 (ICE in assign_by_spills, at lra-assigns.c:1417 (error...
authorVladimir Makarov <vmakarov@redhat.com>
Fri, 8 Jul 2016 20:29:12 +0000 (20:29 +0000)
committerVladimir Makarov <vmakarov@gcc.gnu.org>
Fri, 8 Jul 2016 20:29:12 +0000 (20:29 +0000)
commitd13835b668ac64ae062fa0c765476d229b6b2c22
tree551ccc60f40d8af6047c0898eeac69b17fcdf3b6tree | snapshot
parent65a550b46e5d9759fae0e5af17a494e1f9f5d821commit | diff
re PR rtl-optimization/71621 (ICE in assign_by_spills, at lra-assigns.c:1417 (error: unable to find a register to spill) w/ -O2 -mavx2 -ftree-vectorize)

2016-07-08  Vladimir Makarov  <vmakarov@redhat.com>

PR rtl-optimization/71621
* lra-constraints.c (process_alt_operands): Check combination of
reg class and mode.

2016-07-08  Vladimir Makarov  <vmakarov@redhat.com>

PR rtl-optimization/71621
* gcc.target/i386/pr71621-1.c: New.
* gcc.target/i386/pr71621-2.c: New.

From-SVN: r238178
gcc/ChangeLog diff | blob | history
gcc/lra-constraints.c diff | blob | history
gcc/testsuite/ChangeLog diff | blob | history
gcc/testsuite/gcc.target/i386/pr71621-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/i386/pr71621-2.c [new file with mode: 0644] blob
Domain: System / Toolchain;