microblaze: exception: fix unaligned data access register mask
authorOvidiu Panait <ovidiu.panait@windriver.com>
Sun, 13 Feb 2022 08:09:24 +0000 (10:09 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 15 Feb 2022 12:11:43 +0000 (13:11 +0100)
commitd1114b83405ceaccd46bce96001e6da4fab3ae40
tree8ff14c919f2cdf9625c279b1e914b9a19ff630bd
parent339f489d524e8daa40a4ab0c64bfe65ef30f5fc6
microblaze: exception: fix unaligned data access register mask

The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111

 ...
 Hardware exception at 0x111 address
 Unaligned data access exception
 Unaligned word access
 Unaligned store access
 Register R5
 Return address from exception 0x7f99dfc
 ### ERROR ### Please RESET the board ###
"""

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-6-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/microblaze/cpu/exception.c