[X86] ALU/ADC RMW instructions should use the WriteRMW sequence class
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 3 Oct 2018 10:01:13 +0000 (10:01 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 3 Oct 2018 10:01:13 +0000 (10:01 +0000)
commitd11015861c370105d05931c7cfecbf35e6da26e8
treee777635dc7a607c7fd45d7c3ec56af4f61e3258a
parentdb2e641fd76799b5877c614c3db165a92e7e5dfb
[X86] ALU/ADC RMW instructions should use the WriteRMW sequence class

I was expecting this to be a nfc but Silvermont seems to be setup a little differently:

// A folded store needs a cycle on MEC_RSV for the store data, but it does not need an extra port cycle to recompute the address.
def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;

So moving from WriteStore to WriteRMW reduces predicted port pressure, confirmed by @craig.topper that this is correct.

Differential Revision: https://reviews.llvm.org/D52740

llvm-svn: 343670
llvm/lib/Target/X86/X86Schedule.td
llvm/test/tools/llvm-mca/X86/SLM/resources-x86_64.s