clk: imx: imx6ul: Fix csi clk gate register
authorStefan Riedmueller <s.riedmueller@phytec.de>
Mon, 27 Sep 2021 07:28:57 +0000 (09:28 +0200)
committerAbel Vesa <abel.vesa@nxp.com>
Fri, 1 Oct 2021 07:15:51 +0000 (10:15 +0300)
commitd1012253a2d377f389ea09a82e04b2241fb30b10
treef8eb8c855b665e7d124150cb784523c3171ad6d4
parent2f9d61869640f732599ec36b984c2b5c46067519
clk: imx: imx6ul: Fix csi clk gate register

According to the imx6ul Reference Manual the csi clk gate register is
CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the
Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the
csi clk gate which is the current setting.

Tests have shown though that the correct csi clk gate register for the
imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct
register for both platforms.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Tested-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210927072857.3940880-2-s.riedmueller@phytec.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
drivers/clk/imx/clk-imx6ul.c