[X86] Add the vector integer min/max instructions to isAssociativeAndCommutative.
authorCraig Topper <craig.topper@intel.com>
Wed, 5 Jun 2019 18:25:09 +0000 (18:25 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 5 Jun 2019 18:25:09 +0000 (18:25 +0000)
commitd0fff89b81650e1b7d6c9c73c035672099b0c2db
tree45c5037279072f7f6b6a0137284f8bcaa67dcf4b
parent13dd125043fa40b2bf1f8b5d3143b20caf6c68c2
[X86] Add the vector integer min/max instructions to isAssociativeAndCommutative.

As far as I know these should be freely reassociatable just like
the floating point MAXC/MINC instructions.

The *reduce* test changes are largely regressions and caused by
the "generic" CPU we default to not having a scheduler model.

The machine-combiner-int-vec.ll test shows the positive benefits
of this change.

Differential Revision: https://reviews.llvm.org/D62787

llvm-svn: 362629
14 files changed:
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
llvm/test/CodeGen/X86/vector-reduce-smax-widen.ll
llvm/test/CodeGen/X86/vector-reduce-smax.ll
llvm/test/CodeGen/X86/vector-reduce-smin-widen.ll
llvm/test/CodeGen/X86/vector-reduce-smin.ll
llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll
llvm/test/CodeGen/X86/vector-reduce-umax.ll
llvm/test/CodeGen/X86/vector-reduce-umin-widen.ll
llvm/test/CodeGen/X86/vector-reduce-umin.ll