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(parent: 8f5a2dd) | patch
oprofile/x86: reserve counter msrs pairwise
authorRobert Richter <robert.richter@amd.com>
Tue, 23 Mar 2010 18:33:21 +0000 (19:33 +0100)
committerRobert Richter <robert.richter@amd.com>
Tue, 4 May 2010 09:35:26 +0000 (11:35 +0200)
commitd0e4120fda6f87eead438eed4d49032e12060e58
tree57f3ab727aa12bc63f19437a0a026e2ea5bd6d67tree | snapshot
parent8f5a2dd83a1f8e89fdc17eb0f2f07c2e713e635acommit | diff
oprofile/x86: reserve counter msrs pairwise

For AMD's and Intel's P6 generic performance counters have pairwise
counter and control msrs. This patch changes the counter reservation
in a way that both msrs must be registered. It joins some counter
loops and also removes the unnecessary NUM_CONTROLS macro in the AMD
implementation.

Signed-off-by: Robert Richter <robert.richter@amd.com>
arch/x86/oprofile/op_model_amd.c diff | blob | history
arch/x86/oprofile/op_model_ppro.c diff | blob | history
Domain: System / Uncategorized;