[VPlan][LV] Introduce condition bit in VPBlockBase
authorDiego Caballero <diego.caballero@intel.com>
Mon, 9 Jul 2018 15:57:09 +0000 (15:57 +0000)
committerDiego Caballero <diego.caballero@intel.com>
Mon, 9 Jul 2018 15:57:09 +0000 (15:57 +0000)
commitd09530144a5412a01d222a77257ab2be12d977f1
tree3cb9a6d79bdda57b84a0fa940a5507a1b5682ab4
parent48db19e95a711d0a0e0f7ed835f9bfcb2c1b4892
[VPlan][LV] Introduce condition bit in VPBlockBase

This patch introduces a VPValue in VPBlockBase to represent the condition
bit that is used as successor selector when a block has multiple successors.
This information wasn't necessary until now, when we are about to introduce
outer loop vectorization support in VPlan code gen.

Reviewers: fhahn, rengolin, mkuper, hfinkel, mssimpso

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D48814

llvm-svn: 336554
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/lib/Transforms/Vectorize/VPlan.cpp
llvm/lib/Transforms/Vectorize/VPlan.h
llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp