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pan/bi: Add staging register counts to ISA.xml
authorAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Wed, 23 Dec 2020 16:30:17 +0000 (11:30 -0500)
committerMarge Bot <eric+marge@anholt.net>
Wed, 23 Dec 2020 17:06:57 +0000 (17:06 +0000)
commitcffc1d90da0d03e1ec90b1fff2e35cc0f5fee390
tree5159526083b696f404b9d34d01eca485b6a07875tree | snapshot
parentfaa18708d1d3a162e2cc6d7649d87b3e33d3b243commit | diff
pan/bi: Add staging register counts to ISA.xml

Message-passing instructions that read/write staging registers access
either:

* a fixed number of registers
* vecsize registers (/2 for LD/ST_CVT if register_format is 16-bit)
* a computed number for TEXC

This adds the fixed counts into the XML for the first type and space to
specify the latter types.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8213>
src/panfrost/bifrost/ISA.xml diff | blob | history
src/panfrost/bifrost/isa_parse.py diff | blob | history
Domain: Graphics System / GL;