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[SDAG][AArch64] Boolean and/or reduce to umax/min reduce (PR41635)
authorNikita Popov <nikita.ppv@gmail.com>
Mon, 6 May 2019 16:17:17 +0000 (16:17 +0000)
committerNikita Popov <nikita.ppv@gmail.com>
Mon, 6 May 2019 16:17:17 +0000 (16:17 +0000)
commitcfe786a19567424b04206bea5b5f1817fe9041b4
tree7b1db578324a53136e46d6e920b69c8c7faaffbbtree | snapshot
parentc3167696bc3758efc9c1e98c63ef653951567a2acommit | diff
[SDAG][AArch64] Boolean and/or reduce to umax/min reduce (PR41635)

This addresses one half of https://bugs.llvm.org/show_bug.cgi?id=41635
by combining a VECREDUCE_AND/OR into VECREDUCE_UMIN/UMAX (if latter is
legal but former is not) for zero-or-all-ones boolean reductions (which
are detected based on sign bits).

Differential Revision: https://reviews.llvm.org/D61398

llvm-svn: 360054
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
llvm/test/CodeGen/AArch64/vecreduce-bool.ll diff | blob | history
Domain: System / Toolchain;