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(parent: 0da310e) | patch
riscv: dts: Add DT support for SiFive L2 cache controller
authorYash Shah <yash.shah@sifive.com>
Fri, 3 Jan 2020 04:13:20 +0000 (09:43 +0530)
committerPaul Walmsley <paul.walmsley@sifive.com>
Fri, 3 Jan 2020 08:56:23 +0000 (00:56 -0800)
commitcfda8617e22a8bf217a613d0b3ba3a38778443ba
tree85fbdb2001a712861d788616d17dc654e28740ddtree | snapshot
parent0da310e82d3a9bff6ef6b0f2fbf45d1a05cc64fecommit | diff
riscv: dts: Add DT support for SiFive L2 cache controller

Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
arch/riscv/boot/dts/sifive/fu540-c000.dtsi diff | blob | history
Domain: System / Kernel;