broadcom/compiler: don't predicate postponed spills
authorIago Toral Quiroga <itoral@igalia.com>
Wed, 22 Jun 2022 07:43:30 +0000 (09:43 +0200)
committerMarge Bot <emma+marge@anholt.net>
Tue, 28 Jun 2022 05:49:51 +0000 (05:49 +0000)
commitcfccd93efc95277a739a202a036cbea36fde85f4
treed1345c6accec96c50c5ea428dead68333c2d5a31
parent98420408d0bd0d339c723d6de544a668b2b8f9b6
broadcom/compiler: don't predicate postponed spills

The postponed spill is predicated using the condition from the
last write, but this is only correct if the register was only
written once in the TMU sequence, or if it is always written with
the same predication.

While we could try to track whether this is the case or not, it
would make the postponed spill path even more complex than it
already is, so let's just avoid predicating these. We are already
discouraging TMU spilling of registers in the middle of TMU
sequences, so this should not be a very common case.

Cc: mesa-stable
Reviewed-by: Alejandro PiƱeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17201>
src/broadcom/compiler/vir_register_allocate.c