RISC-V: Add supported for ordered booting method using HSM
authorAtish Patra <atish.patra@wdc.com>
Wed, 18 Mar 2020 01:11:43 +0000 (18:11 -0700)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Tue, 31 Mar 2020 18:27:50 +0000 (11:27 -0700)
commitcfafe260137418d0265d0df3bb18dc494af2b43e
tree50bde642415f253c2f4bf848fcb5441af43f2c79
parentdb5a79460315bd12dedee5f964cd72f3a534ecb2
RISC-V: Add supported for ordered booting method using HSM

Currently, all harts have to jump Linux in RISC-V. This complicates the
multi-stage boot process as every transient stage also has to ensure all
harts enter to that stage and jump to Linux afterwards. It also obstructs
a clean Kexec implementation.

SBI HSM extension provides alternate solutions where only a single hart
need to boot and enter Linux. The booting hart can bring up secondary
harts one by one afterwards.

Add SBI HSM based cpu_ops that implements an ordered booting method in
RISC-V. This change is also backward compatible with older firmware not
implementing HSM extension. If a latest kernel is used with older
firmware, it will continue to use the default spinning booting method.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
arch/riscv/kernel/Makefile
arch/riscv/kernel/cpu_ops.c
arch/riscv/kernel/cpu_ops_sbi.c [new file with mode: 0644]
arch/riscv/kernel/head.S
arch/riscv/kernel/smpboot.c
arch/riscv/kernel/traps.c