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(parent: 0f0e1b5) | patch
[RISCV] Codegen support for memory operations
authorAlex Bradbury <asb@lowrisc.org>
Wed, 8 Nov 2017 12:20:01 +0000 (12:20 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Wed, 8 Nov 2017 12:20:01 +0000 (12:20 +0000)
commitcfa6291bb1ae1d1d66467b662169af9453b7d846
treef270e27c3ec2e0e8e02d59aa0af49a8d0c0e9647tree | snapshot
parent0f0e1b54f07bb63ca8da28399028e2d5387ce500commit | diff
[RISCV] Codegen support for memory operations

This required the implementation of RISCVTargetInstrInfo::copyPhysReg. Support
for lowering global addresses follow in the next patch.

Differential Revision: https://reviews.llvm.org/D29934

llvm-svn: 317685
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.h diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/test/CodeGen/RISCV/mem.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/wide-mem.ll [new file with mode: 0644] blob
Domain: System / Toolchain;