projects / platform / kernel / linux-rpi.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 1558209) | patch
riscv: dts: starfive: visionfive 2: correct spi's ss pin
authorNam Cao <namcao@linutronix.de>
Thu, 12 Oct 2023 09:17:29 +0000 (11:17 +0200)
committerConor Dooley <conor.dooley@microchip.com>
Thu, 12 Oct 2023 09:23:23 +0000 (10:23 +0100)
commitcf98fe6b579e55aa71b6197e34c112b51f0c2a66
tree5ac9434360116e83119f252ba90d41abb0945cf7tree | snapshot
parent1558209533f140624a00408bdab796ab3f309450commit | diff
riscv: dts: starfive: visionfive 2: correct spi's ss pin

The ss pin of spi0 is the same as sck pin. According to the
visionfive 2 documentation, it should be pin 49 instead of 48.

Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration")
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi diff | blob | history
Domain: System / Kernel;