ARM: AM43xx: clocks: Update DPLL details
authorLokesh Vutla <lokeshvutla@ti.com>
Tue, 10 Dec 2013 09:32:20 +0000 (15:02 +0530)
committerTom Rini <trini@ti.com>
Thu, 19 Dec 2013 02:14:01 +0000 (21:14 -0500)
commitcf04d0326bd1e24909cfe644c0c8676440a915b1
treeb0363c4e98bc6eb2bfe4c5bf5c6ef76f40ccaf36
parent4892495e368da9462cd5c1c0d6498fe95b45192e
ARM: AM43xx: clocks: Update DPLL details

Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE  VDD_MPU
OPP50 OPP50
OPP50  OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz

Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
arch/arm/include/asm/arch-am33xx/clock.h
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
board/ti/am43xx/board.c
board/ti/am43xx/board.h
board/ti/am43xx/mux.c