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intel/genxml: Add Gen10 CACHE_MODE_1 definitions
authorAnuj Phogat <anuj.phogat@gmail.com>
Mon, 5 Jun 2017 15:31:01 +0000 (08:31 -0700)
committerAnuj Phogat <anuj.phogat@gmail.com>
Thu, 22 Jun 2017 21:17:45 +0000 (14:17 -0700)
commitceed55e7bba30b60a727309616d6f7e3c2e48a5a
tree75f1fd9cd7a289e86fa0b9fca3ec24c571799278tree | snapshot
parent6338b63270e0676f7524c70fbbf4967e43524bd2commit | diff
intel/genxml: Add Gen10 CACHE_MODE_1 definitions

Few of the fields in this register are changed as compared
to gen9.xml.

V2: Remove some fields which are not valid anymore.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
src/intel/genxml/gen10.xml diff | blob | history
Domain: Graphics System / GL;