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clk: renesas: r8a779g0: Add SCIF clocks
authorGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 7 Oct 2022 13:10:02 +0000 (15:10 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 26 Oct 2022 10:38:01 +0000 (12:38 +0200)
commitceb22d9312b3dcb3568da7ab0d62aea8b8bf0a15
tree8f1e4cc66c096f9be2faf326c404a3142c78fab0tree | snapshot
parentf5684bde0375f4feb2a9ed1c146df29437652e70commit | diff
clk: renesas: r8a779g0: Add SCIF clocks

Add the module clocks used by the Serial Communication Interfaces with
FIFO (SCIF) on the Renesas R-Car V4H (R8A779G0) SoC.

Based on a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/a6ab466cfdac377106494c00b811a60151cb1825.1665147497.git.geert+renesas@glider.be
drivers/clk/renesas/r8a779g0-cpg-mssr.c diff | blob | history
Domain: System / Kernel;