drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write
authorMichał Winiarski <michal.winiarski@intel.com>
Tue, 12 Apr 2016 13:51:55 +0000 (15:51 +0200)
committerMika Kuoppala <mika.kuoppala@intel.com>
Wed, 13 Apr 2016 12:34:51 +0000 (15:34 +0300)
commitce81a65c79d6012a384563caf76d47e28947a347
treec59365e9a7c81d279139b6ed86bed4d16b10fa2e
parent97ea6be161c55dec896b65c95157d953c330ae05
drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

We started to use PIPE_CONTROL to write render ring seqno in order to
combat seqno write vs interrupt generation problems. This was introduced
by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt
generation on gen8+ execlists").

On gen8+ size of PIPE_CONTROL with Post Sync Operation should be
6 dwords. When we're using older 5-dword variant it's possible to
observe inconsistent values written by PIPE_CONTROL with Post
Sync Operation from user batches, resulting in rendering corruptions.

v2: Fix BAT failures
v3: Comments on alignment and thrashing high dword of seqno (Chris)
v4: Updated commit msg (Mika)

Testcase: igt/gem_pipe_control_store_loop/*-qword-write
Issue: VIZ-7393
Cc: stable@vger.kernel.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460469115-26002-1-git-send-email-michal.winiarski@intel.com
drivers/gpu/drm/i915/intel_lrc.c