[RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits...
authorCraig Topper <craig.topper@sifive.com>
Tue, 11 May 2021 16:32:19 +0000 (09:32 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 11 May 2021 16:42:48 +0000 (09:42 -0700)
commitce6e4f27dd72f834502f47176d84869a1f509d7b
tree9e1e19153b3764f7d2ccd76df21ff315957cb203
parent5f78ba001ca23ab826b9be823fc8ac0a0e5d2237
[RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

My thought process is that if v2i64 is an LMUL=1 type then v2i32
should be an LMUL=1/2 type. We limit the fractional LMUL so that
SEW=64 clips to LMUL=1, SEW=32 clips to LMUL=1/2, etc. This
ensures there's always a fractional LMUL available to truncate a type.
This does reduce the number of vsetvlis in some cases.

Some tests increase vsetvlis because the best container type for a
mask type is dependent on the LMUL+SEW that the mask was produced
from, but you can't tell that from the type. I think this is
something we need to solve this in the machine IR when optimizing
vsetvlis.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D101215
58 files changed:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll