[AMDGPU] Introduce never uniform bit field in tablegen
authorYashwant Singh <Yashwant.Singh@amd.com>
Wed, 8 Feb 2023 06:11:51 +0000 (11:41 +0530)
committerYashwant Singh <Yashwant.Singh@amd.com>
Wed, 8 Feb 2023 06:15:48 +0000 (11:45 +0530)
commitcde2f330b36fc36760329be1d3c52e92da400663
treed1b18b037430437e54b333999dc639a6dc9ebe2a
parent1cf344d9465a924536f548e87386977ea5cf908c
[AMDGPU] Introduce never uniform bit field in tablegen

IsNeverUniform can be set to 1 to mark instructions which are
inherently never-uniform/divergent. Enabling this bit in
Writelane instruction for now. To be extended to all required
instructions.

Reviewed By: arsenm, sameerds, #amdgpu

Differential Revision: https://reviews.llvm.org/D143154
llvm/lib/Target/AMDGPU/SIDefines.h
llvm/lib/Target/AMDGPU/SIInstrFormats.td
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/VOP2Instructions.td
llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/always-uniform.mir
llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/never-uniform.mir