AMDGPU: Add DS append/consume intrinsics
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 28 Jan 2019 20:14:49 +0000 (20:14 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 28 Jan 2019 20:14:49 +0000 (20:14 +0000)
commitcdd191d9db6a17b75b5f6d6f3d1d2691ac198153
tree3ade69542218a8b35a4658c843389b8a1fd01274
parente4e9ba2bea60c73a19d8a673e947f0d9b258a777
AMDGPU: Add DS append/consume intrinsics

Since these pass the pointer in m0 unlike other DS instructions, these
need to worry about whether the address is uniform or not. This
assumes the address is dynamically uniform, and just uses
readfirstlane to get a copy into an SGPR.

I don't know if these have the same 16-bit add for the addressing mode
offset problem on SI or not, but I've just assumed they do.

Also includes some misc. changes to avoid test differences between the
LDS and GDS versions.

llvm-svn: 352422
llvm/include/llvm/IR/IntrinsicsAMDGPU.td
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.append.ll [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.consume.ll [new file with mode: 0644]