clk: mmp: add mmp private gate clock
authorChao Xie <chao.xie@marvell.com>
Fri, 31 Oct 2014 02:13:46 +0000 (10:13 +0800)
committerMichael Turquette <mturquette@linaro.org>
Thu, 13 Nov 2014 00:34:00 +0000 (16:34 -0800)
commitcdce35460f5bd929cbcb75a8f436776bd0112f49
tree00f8559dd38991327e643c86701c83faf5ceff4c
parentee81f4ee2a3632a2d7928f680c4af8243a18762f
clk: mmp: add mmp private gate clock

Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. It is not always that "1" is to enable while "0" is to disable
   when write register.

So we have to define the "mask", "enable_val", "disable_val" for
this kind of gate clock.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
drivers/clk/mmp/Makefile
drivers/clk/mmp/clk-gate.c [new file with mode: 0644]
drivers/clk/mmp/clk.h