clk: imx8mq: add 27m phy pll ref clock
authorPeng Fan <peng.fan@nxp.com>
Fri, 25 Feb 2022 09:00:02 +0000 (17:00 +0800)
committerAbel Vesa <abel.vesa@nxp.com>
Thu, 7 Apr 2022 08:04:11 +0000 (11:04 +0300)
commitcdc86e473b353c8a026a337ee9fb9e1fbbe2276b
treee2a1c0531c428e0ecfbeecb83d21c43389effc4b
parent3123109284176b1532874591f7c81f3837bbdc17
clk: imx8mq: add 27m phy pll ref clock

According to pll documentation, the 3rd pll ref clock should be
hdmi phy 27m clock, not dummy clock.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225090002.2497057-3-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
drivers/clk/imx/clk-imx8mq.c