projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: d40dd6b) | patch
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
authorCraig Topper <craig.topper@sifive.com>
Mon, 26 Jun 2023 04:59:27 +0000 (21:59 -0700)
committerCraig Topper <craig.topper@sifive.com>
Mon, 26 Jun 2023 04:59:27 +0000 (21:59 -0700)
commitcdb91465e34d12b22c143847eb5fdb278ecf7689
tree93cf8c30e9be6803349ff20c0c1c1c0e763f6be2tree | snapshot
parentd40dd6be00d881a13a881f02ffa10b48d1441615commit | diff
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.

It was only used for the compressed instruction c.jr which expands
to jalr with rd=x0. Use WriteJalr instead to match jalr.
llvm/lib/Target/RISCV/RISCVInstrInfoC.td diff | blob | history
llvm/lib/Target/RISCV/RISCVSchedRocket.td diff | blob | history
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td diff | blob | history
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td diff | blob | history
llvm/lib/Target/RISCV/RISCVSchedule.td diff | blob | history
Domain: System / Toolchain;