ath9k: do not set half/quarter channel flags in AR_PHY_MODE
authorFelix Fietkau <nbd@openwrt.org>
Sat, 22 Feb 2014 13:52:48 +0000 (14:52 +0100)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 24 Feb 2014 20:38:38 +0000 (15:38 -0500)
commitcd6cfd7311a385144a2f9c74f692ae2df3ae033f
tree4bab6067af1eeab44a9511ce0ea023f2bc3482cc
parent2120ac96744f9517f19241b7c0adb796eeb53eb6
ath9k: do not set half/quarter channel flags in AR_PHY_MODE

5/10 MHz channel bandwidth is configured via the PLL clock, instead of
the AR_PHY_MODE register. Using that register is AR93xx specific, and
makes the mode incompatible with earlier chipsets.

In some early versions, these flags were apparently applied at the wrong
point in time and thus did not cause connectivity issues, however now
they are causing problems, as pointed out in this OpenWrt ticket:

https://dev.openwrt.org/ticket/14916

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_phy.c