[FastISel][AArch64] Fix sign-/zero-extend folding when SelectionDAG is involved.
authorJuergen Ributzka <juergen@apple.com>
Tue, 14 Oct 2014 20:36:02 +0000 (20:36 +0000)
committerJuergen Ributzka <juergen@apple.com>
Tue, 14 Oct 2014 20:36:02 +0000 (20:36 +0000)
commitcd11a2806bd676ed788d5a6aaf7e9e3075be00d6
tree6ead8fb13bddbc96036b6a9fe794ab7bf2ce2b8f
parentca0a38e0ae28a31eb73a58c2262cd8214898b738
[FastISel][AArch64] Fix sign-/zero-extend folding when SelectionDAG is involved.

Sign-/zero-extend folding depended on the load and the integer extend to be
both selected by FastISel. This cannot always be garantueed and SelectionDAG
might interfer. This commit adds additonal checks to load and integer extend
lowering to catch this.

Related to rdar://problem/18495928.

llvm-svn: 219716
llvm/lib/Target/AArch64/AArch64FastISel.cpp
llvm/test/CodeGen/AArch64/fast-isel-int-ext2.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/fast-isel-int-ext3.ll [new file with mode: 0644]