drm/msm/a6xx: Add A610 speedbin support
authorKonrad Dybcio <konrad.dybcio@linaro.org>
Thu, 15 Jun 2023 23:21:01 +0000 (01:21 +0200)
committerRob Clark <robdclark@chromium.org>
Sun, 18 Jun 2023 18:35:27 +0000 (11:35 -0700)
commitcd036d542afb82adfbbd43c5dbeb7010e8e91ee7
tree4dfa15bbaebdff66a939faaebfd28ed5d145dd29
parent20c8e39985b9a4442123e0fa6496183d9418e422
drm/msm/a6xx: Add A610 speedbin support

A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542780/
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/adreno/a6xx_gpu.c