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(parent: 4718a47) | patch
cxgb4: add error handlers to LE intr_handler
authorRaju Rangoju <rajur@chelsio.com>
Tue, 25 Aug 2020 03:55:46 +0000 (09:25 +0530)
committerDavid S. Miller <davem@davemloft.net>
Tue, 25 Aug 2020 13:07:44 +0000 (06:07 -0700)
commitcca852831c0672e1b2da590c23764b5ad149cbb7
tree6e21abc024ffb17ae388b0b7f3cf550cb23849c1tree | snapshot
parent4718a471f1a7fc5cc943377c09300bb35138daf9commit | diff
cxgb4: add error handlers to LE intr_handler

cxgb4 does not look for HASHTBLMEMCRCERR and CMDTIDERR
bits in LE_DB_INT_CAUSE register, but these are enabled
in LE_DB_INT_ENABLE. So, add error handlers to LE
interrupt handler to emit a warning or alert message
for hash table mem crc and cmd tid errors

Signed-off-by: Raju Rangoju <rajur@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c diff | blob | history
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h diff | blob | history
Domain: System / Kernel;