drm/amd/display: Avoid unnecessary pixel rate divider programming
authorTaimur Hassan <Syed.Hassan@amd.com>
Tue, 13 Sep 2022 22:35:20 +0000 (18:35 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 29 Sep 2022 13:41:45 +0000 (09:41 -0400)
commitcc8dee689a6bced98c8bd83ffbf4b2041641a860
tree15095706b46322afd4d63ba0b2d6c6cd4f2fbc30
parent17caab0f0b47d53ad02e20673b51f30a6a16025a
drm/amd/display: Avoid unnecessary pixel rate divider programming

[Why]
Programming pixel rate divider when FIFO is enabled can cause FIFO error.

[How]
Skip divider programming when divider values are the same to prevent FIFO
error.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c