AMDGPU: Fix SILoadStoreOptimizer for gfx90a
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 10 May 2021 13:22:45 +0000 (09:22 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 12 May 2021 01:26:43 +0000 (21:26 -0400)
commitcc79aaced0a405c7448c832a0974a694494496ca
tree3811e668627fd16c804ef14b866b962a3e9e0119
parent0f2eb7e6e5dc2c1b5d1080160733b3a49e00c99c
AMDGPU: Fix SILoadStoreOptimizer for gfx90a

This was hardcoding the register class to use for the newly created
pointer registers, violating the aligned VGPR requirement.
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll