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[SVE][CodeGen] Improve codegen for some zero-extends of masked loads
authorDavid Sherwood <david.sherwood@arm.com>
Thu, 13 Jul 2023 15:21:31 +0000 (15:21 +0000)
committerDavid Sherwood <david.sherwood@arm.com>
Mon, 17 Jul 2023 08:19:27 +0000 (08:19 +0000)
commitcc68e05bd2cc477f7286b5b566558e990f0e5075
tree9e5cc93f8e8613d77300122f260503c1add75993tree | snapshot
parentb5bcd4f60ba3cbed05459e11d176a3f194145732commit | diff
[SVE][CodeGen] Improve codegen for some zero-extends of masked loads

When doing a masked load of an illegal unpacked type and then
zero-extending to some illegal wider types we sometimes end up
with pointless 'and' instructions that are trying to zero bits
that we already know are zero. This patch fixes that by adding
more cases to performSVEAndCombine.

Differential Revision: https://reviews.llvm.org/D155281
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/sve-intrinsics-mask-ldst-ext.ll diff | blob | history
Domain: System / Toolchain;