llvm-reduce: Add cloning of target MachineFunctionInfo
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 16 Apr 2022 02:35:53 +0000 (22:35 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 7 Jun 2022 14:14:48 +0000 (10:14 -0400)
commitcc5a1b3dd9039d50f6b9caa679d60398f0cec65f
tree1181a5ad63acc0163e21f54b677554d1ade93b35
parentcfe516849907da762c40d7dea2b6c2256d264c48
llvm-reduce: Add cloning of target MachineFunctionInfo

MIR support is totally unusable for AMDGPU without this, since the set
of reserved registers is set from fields here.

Add a clone method to MachineFunctionInfo. This is a subtle variant of
the copy constructor that is required if there are any MIR constructs
that use pointers. Specifically, at minimum fields that reference
MachineBasicBlocks or the MachineFunction need to be adjusted to the
values in the new function.
42 files changed:
llvm/include/llvm/CodeGen/MachineFunction.h
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/lib/Target/ARC/ARCMachineFunctionInfo.cpp
llvm/lib/Target/ARC/ARCMachineFunctionInfo.h
llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
llvm/lib/Target/AVR/AVRMachineFunctionInfo.h
llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h
llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp
llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h
llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.cpp
llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h
llvm/lib/Target/LoongArch/LoongArchMachineFunctionInfo.h
llvm/lib/Target/M68k/M68kMachineFunction.cpp
llvm/lib/Target/M68k/M68kMachineFunction.h
llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.cpp
llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h
llvm/lib/Target/Mips/MipsMachineFunction.cpp
llvm/lib/Target/Mips/MipsMachineFunction.h
llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h
llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp
llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp
llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
llvm/lib/Target/Sparc/SparcMachineFunctionInfo.cpp
llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h
llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp
llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h
llvm/lib/Target/VE/VEMachineFunctionInfo.cpp
llvm/lib/Target/VE/VEMachineFunctionInfo.h
llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
llvm/lib/Target/X86/X86MachineFunctionInfo.cpp
llvm/lib/Target/X86/X86MachineFunctionInfo.h
llvm/lib/Target/XCore/XCoreMachineFunctionInfo.cpp
llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h
llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir [new file with mode: 0644]
llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-riscv.mir [new file with mode: 0644]
llvm/tools/llvm-reduce/ReducerWorkItem.cpp