drm/i915: Add Wa_1409120013:icl,ehl
authorMatt Roper <matthew.d.roper@intel.com>
Wed, 12 Jun 2019 18:36:31 +0000 (11:36 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Fri, 14 Jun 2019 14:24:39 +0000 (07:24 -0700)
commitcc49abc2460fadcc5fc8ec703538100405a405d4
tree2a2eaf2e7afa21609895fce0b72dd5e52ef2a8c1
parent84383d2e8d7c50dc344a1acf7b5b4d32cd1569fc
drm/i915: Add Wa_1409120013:icl,ehl

This chicken bit should be set before enabling FBC to avoid screen
corruption when the plane size has odd vertical and horizontal
dimensions.  It is safe to leave the bit set even when FBC is disabled.

v2:
 - The bspec's name for this bit on these platforms ("Spare 14") is
   pretty meaningless.  Let's rename the bit definition to something
   that more accurately reflects what the bit really does.  (Clint)

v3:
 - The chicken register was already defined (along with a few other
   gen9-specific bits) farther down.  Just add the new bit definition
   there.  (Clint)

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190612183631.30540-1-matthew.d.roper@intel.com
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_fbc.c