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(parent: 0f59b37) | patch
clk: axg: fix 32bit set mpll clk overflow
authorShunzhou Jiang <shunzhou.jiang@amlogic.com>
Mon, 15 Oct 2018 02:47:51 +0000 (10:47 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Tue, 16 Oct 2018 05:44:07 +0000 (22:44 -0700)
commitcc0f619561e3fb81fa89da7b45f4b69296372273
treeb3b70e5436037f11f08778ca4a6837d88c8812dbtree | snapshot
parent0f59b37c5e032aa673e125ae080a6acbdda0d1e2commit | diff
clk: axg: fix 32bit set mpll clk overflow

PD#SWPL-394

Problem:
32bit system clk overflow

Solution:
let mpll clock not overflow

Verify:
gxl

Change-Id: I90c99c026264bb4d6820cd988bd5f8828456e0f6
Signed-off-by: shunzhou.jiang <shunzhou.jiang@amlogic.com>
drivers/amlogic/clk/clk-mpll.c diff | blob | history
drivers/amlogic/clk/gxl/clk_misc.c diff | blob | history
Domain: System / Kernel;