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(parent: 47c8ec8) | patch
llvm-reduce: Don't set generic instruction operands to undef
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 6 Jun 2022 13:21:02 +0000 (09:21 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 7 Jun 2022 14:28:23 +0000 (10:28 -0400)
commitcbbc7e4a7572db4a3ddc008a64f22893220296ef
tree4127f3c37ec9029accedf925e27a80ca0c83ae4btree | snapshot
parent47c8ec811f789ae05970f610217a83347388601bcommit | diff
llvm-reduce: Don't set generic instruction operands to undef

The intention is that these should never have undef operands. It turns
out the restriction the verifier enforces is too lax. The verifier
enforces that registers without a register class cannot be undef, but
it's valid to use a register with a register class and type. The
verifier needs to change to be based on the opcode.
llvm/test/tools/llvm-reduce/mir/generic-vreg.mir diff | blob | history
llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir [new file with mode: 0644] blob
llvm/tools/llvm-reduce/deltas/ReduceRegisterUses.cpp diff | blob | history
Domain: System / Toolchain;