[RISCV] When custom iseling masked stores, copy the mask into V0 instead of virtual...
authorCraig Topper <craig.topper@sifive.com>
Tue, 6 Apr 2021 04:25:52 +0000 (21:25 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 6 Apr 2021 04:28:32 +0000 (21:28 -0700)
commitcb1028a0b95f5f4dd3924d81e8f8d9198b597ff4
tree3d1cd3e7f8b27a0bafba795a9d35879c74948a3d
parent58ccbd0d08fe0a9b4b06d47d0be20f19717919f8
[RISCV] When custom iseling masked stores, copy the mask into V0 instead of virtual register.

I missed a few intrinsics in 3dd4aa7d09599507d1f801ffe4bec4c9eebbb8da
when I did this for masked loads and masked segment loads/stores.

Found while trying to share more code between these custom isel
functions.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll