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[InstCombine] [InstCombine] reduce left-shift-of-right-shifted constant via demanded...
authorSanjay Patel <spatel@rotateright.com>
Tue, 7 Jun 2022 20:54:11 +0000 (16:54 -0400)
committerSanjay Patel <spatel@rotateright.com>
Tue, 7 Jun 2022 22:43:27 +0000 (18:43 -0400)
commitcae993d4c87fa2d0664bb711f100ef7b563f77d9
tree597b7dc38ae3fc5fbff07ac4a8a678aa0490515ftree | snapshot
parent0856a6cb7ad628dc2f352d2126d7b7f9c7e4e9f4commit | diff
[InstCombine] [InstCombine] reduce left-shift-of-right-shifted constant via demanded bits

If we don't demand low bits and it is valid to pre-shift a constant:
(C2 >> X) << C1 --> (C2 << C1) >> X

https://alive2.llvm.org/ce/z/_UzTMP

This is the reverse-order shift sibling to 82040d414b3c ( D127122 ).
It seems likely that we would want to add this to the SDAG version of
the code too to keep it on par with IR.
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp diff | blob | history
llvm/test/Transforms/InstCombine/shift-shift.ll diff | blob | history
Domain: System / Toolchain;