projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b38e78c) | patch
[SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo
authorCraig Topper <craig.topper@sifive.com>
Wed, 23 Mar 2022 16:28:46 +0000 (09:28 -0700)
committerCraig Topper <craig.topper@sifive.com>
Wed, 23 Mar 2022 16:52:07 +0000 (09:52 -0700)
commitcac9773dccd95cd442d2852b7ced0a8a311504f6
tree8e0cf7286a79015b97ae33674f6d4b4d41edd4c9tree | snapshot
parentb38e78cc445c0b6e119e8b3b7e42371caab14a05commit | diff
[SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo

Instead of using operator[], use DenseMap::find to prevent default
constructing an entry if it isn't already in the map.

Also simplify a condition to check for 0 instead of a virtual register.
I'm pretty sure we can only get 0 or a virtual register out of the value
map.
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp diff | blob | history
Domain: System / Toolchain;