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(parent: 5d14b72) | patch
[AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST
authorRon Lieberman <ronlieb.g@gmail.com>
Fri, 16 Nov 2018 01:13:34 +0000 (01:13 +0000)
committerRon Lieberman <ronlieb.g@gmail.com>
Fri, 16 Nov 2018 01:13:34 +0000 (01:13 +0000)
commitcac749ac884cfab87a0b2a805b43530c26a627c8
tree483b52cfd6f80f9842c2ce8132146e9dd1b798e0tree | snapshot
parent5d14b72d5c3f5169fd896ce91378e377f464b18bcommit | diff
[AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST

Add a pass to fixup various vector ISel issues.
Currently we handle converting GLOBAL_{LOAD|STORE}_*
and GLOBAL_Atomic_* instructions into their _SADDR variants.
This involves feeding the sreg into the saddr field of the new instruction.

llvm-svn: 347008
23 files changed:
llvm/lib/Target/AMDGPU/AMDGPU.h diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp diff | blob | history
llvm/lib/Target/AMDGPU/CMakeLists.txt diff | blob | history
llvm/lib/Target/AMDGPU/FLATInstructions.td diff | blob | history
llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp [new file with mode: 0644] blob
llvm/lib/Target/AMDGPU/SIInstrInfo.h diff | blob | history
llvm/lib/Target/AMDGPU/SIInstrInfo.td diff | blob | history
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/ds_write2.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/ds_write2st64.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/global-load-store-atomics.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/global-saddr.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/indirect-addressing-si-pregfx9.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/madak.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/memory_clause.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll diff | blob | history
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