[AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate...
authorAmara Emerson <aemerson@apple.com>
Wed, 3 Jul 2019 01:49:06 +0000 (01:49 +0000)
committerAmara Emerson <aemerson@apple.com>
Wed, 3 Jul 2019 01:49:06 +0000 (01:49 +0000)
commitcac1151845e6b55d38ecac014438e64f8feae687
tree65eb8b8e0a0ac121b668ec8cfb4599d1f11aa90e
parentdfdccbb26ba35ab14e099e8d4d7a6f3150fb3c41
[AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms.

There are two main issues preventing us from generating immediate form shifts:
1) We have partial SelectionDAG imported support for G_ASHR and G_LSHR shift
immediate forms, but they currently don't work because the amount type is
expected to be an s64 constant, but we only legalize them to have homogenous
types.

To deal with this, first we introduce a custom legalizer to *only* custom legalize
s32 shifts which have a constant operand into a s64.

There is also an additional artifact combiner to fold zexts(g_constant) to a
larger G_CONSTANT if it's legal, a counterpart to the anyext version committed
in an earlier patch.

2) For G_SHL the importer can't cope with the pattern. For this I introduced an
early selection phase in the arm64 selector to select these forms manually
before the tablegen selector pessimizes it to a register-register variant.

Differential Revision: https://reviews.llvm.org/D63910

llvm-svn: 364994
17 files changed:
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/lib/Target/AArch64/AArch64LegalizerInfo.h
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h
llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
llvm/test/CodeGen/AArch64/GlobalISel/regbank-shift-imm-64.mir [new file with mode: 0644]
llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir