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(parent: 5be767d) | patch
[ARM] Fix conditions for lowering to S[LR]I
authorPetre-Ionut Tudor <petre-ionut.tudor@arm.com>
Tue, 31 Mar 2020 16:27:45 +0000 (17:27 +0100)
committerPetre-Ionut Tudor <petre-ionut.tudor@arm.com>
Fri, 17 Apr 2020 16:19:24 +0000 (17:19 +0100)
commitcabfcf840a9d15d92466c6774953d3aa399cde92
treea224a15a5a2c4399ac698c1328e138b94e51a1dftree | snapshot
parent5be767d489be9fe0f76f321902f492294444f424commit | diff
[ARM] Fix conditions for lowering to S[LR]I

Summary:
Fixed wrong conditions for generating (S[LR]I X, Y, C2) from
(or (and X, BvecC1), (lsl Y, C2)) and added ISel nodes to lower to S[LR]I. The
optimisation is also enabled by default now.

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77387
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64ISelLowering.h diff | blob | history
llvm/lib/Target/AArch64/AArch64InstrInfo.td diff | blob | history
llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll diff | blob | history
Domain: System / Toolchain;