amd-xgbe: Optimize DMA channel interrupt enablement
authorLendacky, Thomas <Thomas.Lendacky@amd.com>
Fri, 18 Aug 2017 14:03:17 +0000 (09:03 -0500)
committerDavid S. Miller <davem@davemloft.net>
Fri, 18 Aug 2017 23:30:16 +0000 (16:30 -0700)
commitcaa575afad73ce1a40848543461667c57a1ad989
tree82a71d9a5a881bb70031e77818a5cbaa023fa276
parent40452f0ec84a3b7082a934404783a121d378b990
amd-xgbe: Optimize DMA channel interrupt enablement

Currently whenever the driver needs to enable or disable interrupts for
a DMA channel it reads the interrupt enable register (IER), updates the
value and then writes the new value back to the IER. Since the hardware
does not change the IER, software can track this value and elimiate the
need to read it each time.

Add the IER value to the channel related data structure and use that as
the base for enabling and disabling interrupts, thus removing the need
for the MMIO read.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/amd/xgbe/xgbe-dev.c
drivers/net/ethernet/amd/xgbe/xgbe.h